The present invention relates to removing an upper layer of material from an underlying layer on a semiconductor wafer, and more particularly, to forming highly planarized contact plugs on a semiconductor wafer.
Microelectronic devices are small, complex electronic devices manufactured on a substrate made from glass or a suitable semiconductive material. Typical microelectronic devices have many component layers upon which small components are formed, and several insulator layers that electrically isolate the component layers from one another. The individual components are electrically coupled together by conductive interconnects made from polysilicon, aluminum, tungsten, or other suitable conductive materials.
One type of interconnect is a contact plug that extends substantially vertically through an insulator layer. Contact plugs are fabricated by etching vias through an insulator layer, and then depositing a conductive material into the vias and over the insulator layer. As shown in FIG. 1, for example, a lower layer 20 is covered by an insulator layer 30, and vias 32 are etched through the insulator layer 30. An upper layer of conductive material 40 is then deposited into the vias 32 and over the insulator layer 30. A number of contact plugs 42 are formed in the vias 32 by removing the blanket portion 40(a) of the conductive layer 40 and a small amount of material from the top surface 33 of the insulator layer 30. The contact plugs 42 are thus electrically isolated from one another along the top surface 33 of the insulator layer 30. In use, the contact plugs 42 electrically couple the lower layer 20 to other devices that are subsequently formed on top of the insulator layer 30.
In the competitive semiconductor industry, it is desirable to maximize the throughput of finished wafers. The throughput of fabricating contact plugs is a function of several factors, one of which is the rate at which the blanket portion of the conductive upper layer is removed from the wafer. Because the throughput increases with increasing removal rates, it is generally desirable to maximize the rate at which the conductive material is removed from the wafer.
The finished surface of the wafer, however, must also be uniformly planar so that additional circuit patterns may be accurately focused on top of the contact plugs and the insulator layer. As the density of integrated circuits increases, it is often necessary to accurately focus the critical dimensions of the circuit patterns to better than tolerance of approximately 0.1 xcexcm. Yet, focusing circuit patterns to such small tolerances is very difficult when the distance between the lithographic energy source and the surface of the wafer varies because the wafer is not uniformly planar. Several devices may in fact be defective on a wafer with a non-uniformly planar surface. Therefore, the finished surface of the insulator layer and the contact plugs must be a highly uniform, planar surface.
One existing method for forming contact plugs and other interconnects is to wet etch the upper conductive layer down to the insulator layer. Wet etching processes involve depositing an etching solution onto the conductive layer that dissolves the material of the conductive layer. In spin wet etching, which is a particular type of wet etching process, the etching solution is applied through a scanning dispense station onto the conductive layer as the wafer rotates at a high angular velocity. Wet etching, and particularly spin wet etching, rapidly remove large volumes of material from the upper conductive layer. Spin wet etching accordingly provides a high throughput of finished wafers. However, neither static wet etching nor spin wet etching produces a uniformly planar surface. Wet etching is difficult to control and one region of the wafer may be over-etched while another region may be under-etched. Spin etching removes material across the wafer more uniformly than wet etching, but the etchant still may remove or over-etch an upper layer in specific regions such as contact plugs. Therefore, wet etching techniques are generally undesirable methods for forming contact plugs or other interconnects.
Another existing method for fabricating contact plugs is to planarize the conductive material with a chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) process. In a typical CMP process, a wafer is exposed to an abrasive medium under controlled chemical, pressure, velocity, and temperature conditions. Examples of abrasive mediums include slurry solutions and polishing pads. The slurry solutions generally contain small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. The polishing pads are generally planar pads made from a relatively porous material, and they may also contain abrasive particles to abrade the wafer. Thus, when the polishing pad and the wafer move with respect to each other, material is removed from the surface of the wafer mechanically by the abrasive particles in the pad and/or the slurry, and chemically by the chemicals in the slurry. CMP processes are highly desirable because they produce a uniformly planar surface on the wafer. However, compared to wet etching techniques, CMP processes remove material from the wafer at a much slower rate. Thus, CMP processes are time-consuming and have a lower throughput than wet etching techniques.
In light of the problems with existing methods for forming contact plugs and other interconnects on a semiconductor wafer, it would be desirable to develop a method that produces a uniformly planar surface on the wafer while maintaining a high throughput of finished wafers.
The present invention is a method for removing a portion of an upper layer of material from an underlying layer to form a uniformly planar surface on a semiconductor wafer. In accordance with one embodiment of the invention, an upper section of the upper layer is etched to an intermediate point in the upper layer that may be above, below, or flush with a top surface of the underlying layer. The etching step removes the upper section of the upper layer and leaves only a lower section of the upper layer on the wafer. The lower section of the upper layer is then planarized to a final endpoint. The etching step preferably moves the majority of the upper layer from the wafer so that the remaining portion of the upper layer is just thick enough to allow the planarizing step to produce a uniformly planar surface on the wafer.
The etching step is preferably a spin wet etching process in which an etching solution is deposited onto the upper layer while the wafer rotates at a relatively high angular velocity. The centrifugal force generated by the wafer spreads the etching solution across the upper layer to enhance the uniformity of the removal of material from the upper layer. The position at which the etching solution is deposited onto the polishing pad and the scanning of the dispensing position over the polishing pad are preferably controlled to enhance the uniformity of the spin etching step. The planarizing step is preferably a CMP process in which the upper layer is pressed against a polishing medium, and at least one of the wafer or the polishing medium is moved with respect to the other to planarize the upper layer to a uniformly planar surface.